Hey folks,
Decided to tank the current component values in my design and just try a basic Low-Pass Filter with component values I used more frequently in Circuit II last Spring. Used 470k ohm resistors and 390 nanofarad capacitor. Not surprisingly the circuit worked! Tested it in the lab and in PSPICE. Cutoff Frequency around 900 hz. Unlike the schematic I provided, the voltage source was set to 0.
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Prototype 2. V7 is varied to change overall feedback resistance |
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Transient Analysis of Prototype 2. Input (Red) of 870 hz. Output (Green). Output is approx 70% of input at calculated cutoff frequency. Behaves as expected. |
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Frequency response of Prototype 2. Corner Frequency around 900 hz. |
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Top: Input of 870 hz. Bottom: Output - As you can see the output is attenuated approximately 70% of the input. Exactly what is expected by the design. |
As I mentioned earlier, the V7 voltage source is what "sets" the "resistance" of the FET. Applying a voltage opens the pathway between the source and drain. Here's the problem. I've learned that for some reason using small resistances for an active LPF does not work. It just doesn't behave like a filter. Not sure why... The current FET I'm using (TIS74) can only vary between 30 to 800 ohms. Adding 800 ohms to 470000 is not going to make much of a significant change in cutoff frequency. I doubt I would even see noticeable change if I implemented this.
I already tried simulation with the FET resistance on. Quite unsuccessful. Circuit does some weird stuff. For voltages between 0 and 2.8, I get the output seen above. However, Once V7 is around 3 volts the entire output is shifted down by about 0.4 volts. I don't know what model transistor PSPICE uses... But I'm thinking it's acting like a switch (like FET's are usually used for). Once a certain point is reached it completely opens/closes the drain/source path. What I'm looking for is a gradual shift in resistance. Since I don't have a TIS74 PSPICE model (and I'm not equipped to program one!) simulation might be futile for this design.
Here's the output with V7 set to 3 volts:
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FET biasing voltage set to 3 volts. Basically drops the output by some constant. No good. |
-Mark